1. Field of the Invention
The present disclosure generally relates to compact FDSOI devices with Bulex areas for back-bias at advanced technology nodes.
2. Description of the Related Art
For next generation technologies, SOI (semiconductor-on-isolator) technology is an attractive candidate to push forward the frontiers imposed by Moore's law. Particularly, fully depleted SOI (FDSOI) techniques seem to provide promising technologies that allow the fabrication of semiconductor devices at technology nodes of 28 nm and beyond. Aside from FDSOI techniques allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, the fabrication processes, as employed in FDSOI techniques, are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques.
In general, a MOSFET as fabricated by SOI techniques is a semiconductor device (MOSFET) in which a semiconductor layer, such as silicon, germanium or silicon germanium, is formed on an insulator layer, e.g., a buried oxide (BOX) layer, which is in turn formed on a semiconductor substrate. Conventionally, there are two types of SOI devices: PDSOI (partially depleted SOI) and FDSOI MOSFETs. For example, in an N-type PDSOI MOSFET, a P-type film being sandwiched between a gate oxide (GOX) and a buried oxide (BOX) is so large that the depletion region cannot cover the whole P-region. Therefore, to some extent, PDSOI devices behave like bulk MOSFETs.
In contrast, the depletion region covers the whole semiconductor layer in an FDSOI device. As the GOX in FDSOI techniques supports fewer depletion charges than the bulk, an increase in inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds.
In recent attempts to provide a simple way of meeting power/performance targets, back-biasing was suggested for FDSOI devices. Herein, back-biasing consists of applying a voltage just under the BOX of target semiconductor devices. In doing so, the electrostatic control of the semiconductor device is changed and the threshold voltage is shifted to either obtain more drive current (hence, higher performance) at the expense of increased leakage current (forward back bias, FBB) or to cut leakage current at the expense of reduced performance. While back bias in planar FDSOI techniques is somewhat similar to body bias as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level and efficiency of the bias that may be applied. For example, back-biasing can be utilized in a dynamic way on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
The publication “UTBB FDSOI Transistors with Dual STI for a MultiVt Strategy at 20 nm Node and Below” by Grenouillet et al. (published in Electron Devices Meeting (IEDM), 2012 IEEE International, IEEE, December 2012, pages 3.6.1-3.6.4) shows a back gate architecture in FDSOI technology with standard SOI wafers, where back bias contacts are implemented via silicide contacts formed in bulk exposed areas located adjacent to SRAM and logic MOSFET devices.
In the following, a known semiconductor device structure will be described with regard to FIG. 1. The illustrated semiconductor device structure has two MOSFET devices 1 and 2 which are provided in accordance with FDSOI techniques. Each of the MOSFET devices 1 and 2 is formed by a gate electrode disposed on an active semiconductor layer 3 of an SOI substrate as described above, particularly over a BOX layer 4 and a base substrate 5. Well portions 6 and 7 are formed within the base substrate 5.
The MOSFET devices 1 and 2 are separated by an isolation element 8, such as a shallow trench isolation (STI) element, which is formed between the MOSFET devices 1 and 2. Furthermore, the MOSFET devices 1 and 2 are laterally enclosed by a deep STI structure 9.
In order to provide a back-bias contact, a bulk-exposed region 10 (also referred to as bulex) is provided for contacting the doped well region 6 in the base substrate 5. Contacts and silicide regions are not shown in FIG. 1. The bulex area 10 is conventionally formed by locally removing the active semiconductor layer 3 and the BOX layer 4 so as to expose an upper surface of the base substrate 5. In accordance with current bulex/hybrid area modules as employed in the fabrication process of FDSOI device structures, bulex areas having a lateral extension of 150 nm in the cross section illustrated in FIG. 1 are formed.
In view of the above-described prior art, it is, therefore, desirable to provide compact SOI, e.g., FDSOI, devices at advanced technology nodes, e.g., 28 nm and beyond, with back bias contact structures, where the integration density may be further increased despite having to provide for or allow for the area necessary for the formation of the back bias contact.